LTspice Monte Carlo: Let Flux Check Your 3.3 V Rail

Flux can simulate your 3.3 V rail and compare component-value cases for you. Describe your circuit, component values, and source conditions in chat. Flux uses ngspice for its built-in circuit simulations and returns operating-point values, waveforms, and plots. Ask it to compare the results with your rail limits using its circuit simulation workflow.

For the 3.3 V rail in an industrial measurement device, ask Flux:

Simulate a feedback circuit with Vout = Vref × (1 + Rtop/Rbottom). Use a 1.25 V reference, a 16.4 kΩ top resistor, and a 10 kΩ bottom resistor. Report the nominal DC output. Compare the high-output case at 1.26875 V, 16.564 kΩ, and 9.9 kΩ with the low-output case at 1.23125 V, 16.236 kΩ, and 10.1 kΩ. Check both outputs against the 3.2175 V to 3.3825 V limits.

Flux is an AI hardware engineer. It can run these circuit checks from a description or your project schematic, then help you continue into the board and enclosure design. The LTspice steps below work through the tolerance problem with reusable netlists: nominal output, 1,000 random trials, all eight worst-case corners, and a resistor-selection decision.

To run Monte Carlo analysis in LTspice, give component values an mc(nominal, tolerance) expression, repeat the simulation with .step, and record one measurement per run with .meas. The tolerance is a fraction: mc(10k, 0.01) samples a 10 kΩ resistor uniformly between 9.9 kΩ and 10.1 kΩ.

Run LTspice on a Flux computer

You can also ask Flux to install and run the engineering tools your team uses on its Windows or Linux cloud computers. For LTspice, ask Flux to set up a Windows computer through the bring-your-own-software workflow.

Download the three netlists in this guide and attach them to your Flux project. Then ask:

Set up a Windows computer with LTspice. Run the attached nominal, Monte Carlo, and corner netlists for this 3.3 V feedback circuit. Compare the measured outputs with the 3.2175 V to 3.3825 V limits. Save the tested computer setup so our team can use it in future projects.

The steps below explain the LTspice setup and how to interpret the results.

1. Define the circuit and its pass/fail limits

Use the standard feedback relationship Vout = Vref × (1 + Rtop/Rbottom). Rtop connects the output to the feedback node. Rbottom connects that node to ground. This is the same type of feedback model used in Analog Devices' statistical tolerance analysis tutorial.

Keep these limits fixed when you compare parts. For this exercise, sample the reference and the two resistors independently with uniform distributions. Record that assumption with the results. A part's tolerance specifies its limits; the production distribution and correlations come from supplier data and measurements.

This test answers a specific question: how reference and resistor variation move the DC setpoint. Give ripple, load transients, and temperature drift their own budgets and tests.

2. Paste this reusable LTspice Monte Carlo netlist

Save the following text as feedback-monte-carlo.cir, open it in LTspice, and select Run. You can also download the Monte Carlo netlist.

* 3.3 V feedback setpoint: independent uniform tolerances
.param tr=0.01 tref=0.015
Vref ref 0 {mc(1.25,tref)}
Ereg out 0 ref fb 1e6
Rtop out fb {mc(16.4k,tr)}
Rbottom fb 0 {mc(10k,tr)}
Rload out 0 1k
.step param run 1 1000 1
.tran 0 1m 0 10u
.meas tran vout FIND V(out) AT=1m
.meas tran pass PARAM if(vout>=3.2175,if(vout<=3.3825,1,0),0)
.end

Ereg is a voltage-controlled voltage source with gain 1,000,000. It drives the output so that the feedback node approaches the reference voltage. This makes a compact DC feedback model. Its finite gain gives a nominal result of about 3.299991 V, less than 9 µV below the ideal 3.300 V result.

• mc(16.4k,tr): samples Rtop from 16.236 kΩ to 16.564 kΩ. Each component has its own random expression.
• .step param run 1 1000 1: requests 1,000 trials. run is a counter, not a component value or a percentage. The counter does not need to appear elsewhere.
• .tran: provides a short, constant-output trace for each trial. The 1 ms endpoint is a measurement time, not a regulator settling-time result.
• vout: records one output value per trial.
• pass: records 1 for an in-range output and 0 for an out-of-range output.

In a schematic, put the expressions in each component's Value field, including the braces. Add the .param, .step, .tran, and .meas lines as SPICE directives. The text netlist gives you the same test without drawing the schematic first.

3. Establish the nominal result first

Before you inspect the random trials, run the nominal circuit. Replace the three sampled values with 1.25, 16.4k, and 10k. Remove the .step line. Keep the measurement and pass/fail lines. The nominal netlist includes those changes.

Expect approximately 3.299991 V and pass = 1. A different nominal result is a reason to check the divider connections and resistor order before you add variation. The resistor ratio is Rtop/Rbottom, not its inverse.

4. Read the measurements, then build a histogram

Return to the Monte Carlo netlist and run it. Open the SPICE Error Log from LTspice's View menu. The log includes measurement tables for vout and pass, one row per step. The log's name does not mean the run failed.

1. Check that each table has 1,000 trial results.
2. Right-click the log and select Plot .step'ed .meas data to inspect output versus trial number.
3. Copy the vout measurement table into a spreadsheet. Select its voltage column and make a histogram, for example with 40 equal-width bins.
4. Calculate minimum, maximum, mean, and standard deviation for the voltage column. Sum the pass column and divide by 1,000 to calculate the sampled pass fraction.
5. Add the 3.2175 V and 3.3825 V specification limits to the chart. Count outputs below and above those limits separately.

As a scale check, a first-order calculation gives an output standard deviation of about 33.1 mV under these independent uniform assumptions. For each input, divide its half-range by √3. The voltage contributions are 49.5 mV from the reference and 20.5 mV from each resistor before that division. Thus σout ≈ √(49.5² + 20.5² + 20.5²)/√3 mV.

A Monte Carlo run can look acceptable even when an allowed corner fails. The sampled pass fraction estimates behavior under the selected distributions; the endpoint test below answers whether every allowed combination meets the DC limit.

For repeatable comparisons, leave Use the clock to reseed the MC generator off in LTspice's settings. Keep the netlist, trial count, and settings with the report. Analog Devices explains the repeatability behavior in Are Random Numbers in LTspice Truly Random?

5. Run the eight worst-case corners

Three independently bounded inputs have 2³ = eight endpoint combinations. For this monotonic equation, the highest output uses a high reference, high Rtop, and low Rbottom. The lowest output reverses those choices.

Vout,max = 1.25 × 1.015 × [1 + (16.4 × 1.01)/(10 × 0.99)] = 3.391535 V.

Vout,min = 1.25 × 0.985 × [1 + (16.4 × 0.99)/(10 × 1.01)] = 3.210515 V.

Both exceed the ±2.5% requirement. To simulate the eight combinations, replace the three randomized component lines with these lines:

Vref ref 0 {1.25*kref}
Rtop out fb {16.4k*ktop}
Rbottom fb 0 {10k*kbottom}

Remove the Monte Carlo .step param run line. Add these three nested sweeps instead. Keep Ereg, Rload, and the analysis and measurement directives unchanged. Or use the complete eight-corner netlist.

.step param kref list 0.985 1.015
.step param ktop list 0.99 1.01
.step param kbottom list 0.99 1.01

Expect eight measured outputs. Their endpoints will be within about 10 µV of the ideal-equation values because of the finite feedback gain.

6. Make one change and repeat the tests

Change both feedback resistors to ±0.1%, with the reference still at ±1.5%. In the Monte Carlo netlist, change tr=0.01 to tr=0.001. In the corner netlist, change both resistor sweep lists to 0.999 1.001. Keep the same output limits.

The ideal-equation worst-case range becomes 3.246466 V to 3.353666 V, or approximately −1.62% to +1.63%. That fits inside 3.2175 V to 3.3825 V. The first-order standard deviation falls to about 28.6 mV; reference variation now dominates.

The purchasing decision is clear: ±0.1% resistors close this DC setpoint budget. The device-level budget must also allocate the remaining margin to temperature, load regulation, ripple, and other specified effects. For a matched resistor network, use its ratio-tolerance and tracking specifications to model the pair together.

Uniform Monte Carlo versus Gaussian variation

mc(x,y) uses a uniform distribution, not a bell curve. For a Gaussian model with a standard deviation equal to one-third of the stated fractional tolerance, use an expression such as:

Rtop out fb {16.4k*(1+gauss(0.01/3))}

Here, 1% is a three-sigma span. A Gaussian distribution has tails beyond that span. Choose its sigma from process data, and use the hard tolerance endpoints for the bounded corner test. Do not convert a datasheet's ±1% limit into three sigma by default.

Bring the decision back to the complete device in Flux

The useful output of this LTspice exercise is the requirement and the part change: a 3.3 V rail, a fixed acceptance window, and a feedback pair with a closed tolerance budget. Carry that intent into the design, alongside the measurement board, its connectors, and its enclosure.

Flux's circuit simulation workflow runs SPICE analyses from a project schematic or a circuit you describe. Give Flux the values, source conditions, and measurements you need. Ask it to compare explicit component-value cases with the same operating conditions.

Simulate this feedback circuit with a 1.25 V reference, a 16.4 kΩ top resistor, and a 10 kΩ bottom resistor. Report the DC output. Then compare the high-output case at 1.26875 V, 16.4164 kΩ, and 9.99 kΩ with the low-output case at 1.23125 V, 16.3836 kΩ, and 10.01 kΩ. Compare both outputs with the 3.2175 V to 3.3825 V limits.

The same project can hold the physical device. Flux creates mechanical parts and assemblies around the board and checks fit and clearance. Use the electrical decision to keep the board design moving, then carry the actual board and connector positions into the mechanical work.

Design a serviceable enclosure around this measurement board. Keep the connector openings aligned with the placed connectors. Add mounting bosses and a removable lid. Check board-to-lid clearance and access to the mounting screws.

That connects two engineering decisions in one device: component values that meet the rail requirement and mechanical geometry that fits the assembled board. Explore electronics design with Flux to continue from circuit requirements into the device design.

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Frequently asked questions

How do I run Monte Carlo analysis in LTspice?

What does mc() mean in LTspice?

How many Monte Carlo runs do I need?

Why do repeated LTspice runs give the same random values?

Does Monte Carlo replace worst-case analysis?