Run SPICE on Your Imported Altium and Cadence Boards

Flux runs SPICE on existing circuits in imported Altium and Cadence designs with built-in ngspice. We used a BeagleBone Black reset network and a LimeSDR supply filter to get DC voltage, cutoff frequency, and rise time from the imported circuits.

Import the board. Ask for the response.

The workflow starts with the design you already have. Import it into Flux, identify the circuit question, and ask the AI hardware engineer to select the network, state the model, and run the analyses.

For the six-layer, 459-part BeagleBone Black Rev D Cadence/Allegro import, the question was reset timing:

Simulate the existing reset RC network. Run a DC operating point, an AC sweep, and a transient startup. Report the steady-state voltage, corner frequency, and 10–90% rise time. Explain how the results relate to the imported resistor and capacitor values.

For the 12-layer, 858-part LimeSDR-USB Altium import, the question was supply filtering:

Simulate an existing supply RC filter from this design. Use a 1 mA load. Report the DC output, cutoff frequency, 10–90% rise time, and attenuation at 100 kHz.

1. Read the circuit. Flux identifies the resistor, capacitor, source, and output node in the imported schematic.
2. Run ngspice. It runs the operating point, AC sweep, and transient analysis for the selected network.
3. Explain the results. It reports numerical measurements and connects them to the circuit's RC time constant.

The model behind the measurements

Flux modeled each network with ideal sources, resistors, and capacitors: an unloaded reset RC for BeagleBone Black, and a supply RC with a constant 1 mA load for LimeSDR. Rise time is measured from 10% to 90% of the output step.

The three analyses answer different questions. The DC operating point gives the settled output. The AC sweep gives the small-signal response over frequency. The transient analysis shows how the output changes with time after the input rises.

BeagleBone Black: reset timing

The simulated network is R14 (10 kΩ) and C24 (2.2 µF), driven by an ideal 3.3 V source, with the output measured at C24 pin 1 relative to GND_SIGNAL.

The imported reset network produced 3.300000 V DC, a 7.23 Hz corner, and a 48.3 ms rise time.

For a first-order RC network, the corner frequency is fc = 1 / (2πRC). A 7.23 Hz corner corresponds to a time constant of about 22 ms. The 10–90% rise time is approximately 2.2 × RC, which gives 48.4 ms and agrees with the simulated 48.3 ms.

That turns an imported reset circuit into a timing result. The useful question is no longer just which parts are connected, but how long the reset node takes to rise.

LimeSDR: supply filtering under load

The simulated network is R33 (10 Ω) and C74 (1 µF), with an ideal 1.8 V source on VCC1P8_LMS and the output measured at NetC74_1 relative to ground.

The supply RC produced 1.790 V DC at a 1 mA load, a 15.9 kHz corner, a 22.0 µs rise time, and −16.07 dB at 100 kHz.

The 15.9 kHz corner corresponds to a time constant of about 10 µs. Multiplying by 2.2 predicts a 22 µs rise time. At 100 kHz, the frequency is about 6.3 times the corner, so the first-order low-pass response predicts about −16.1 dB, consistent with the ngspice result.

The DC result answers the load question. The AC result answers the filtering question. The transient result shows the settling speed. Together, they describe the selected circuit more clearly than its component values alone.

Ask a specific circuit question

Start with the network and the decision you need to make. For reset, ask when the node reaches its threshold. For a supply filter, specify the load and the frequency you want to attenuate. Ask Flux to state the model and report the measured quantities.

If your imported board has a first-spin symptom instead, see how Flux diagnosed and corrected a regulator divider on an imported Altium design. That example follows the fault from the symptom through the saved resistor value and BOM.

Source designs: BeagleBone Black by BeagleBoard.org (CC BY-SA 3.0) and LimeSDR-USB by MyriadRF (CC BY 3.0). Screenshots show results from the imported designs.

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